您将学到什么：
- 为什么Nand Flash经常被误解。
- Details about some of the most commonly held NAND flash myths.
- 洞悉NAND闪光灯的重要设计注意事项，包括温度范围，密度，功率等。
Invented by勇back in 1987, NAND flash has fundamentally changed the way we live. Yet, as pervasive as this important technology is, it’s still often misunderstood.
Totally understandable. From temperature range to density to power, the design considerations for NAND flash are many and varied. The depth and breadth of available flash-based products for next-generation storage applications is staggering, and design engineers have questions. We’re here to help.
Keep reading as we dispel some of the most commonly held myths about the transformative technology.
1。QLC flash will replace TLC flash, which replaced MLC flash, which replaced SLC flash.
QLC (quad-level-cell) flash is increasingly becoming visible in the storage industry as solid-state disk (SSD) capacities become bigger and cheaper. While QLC flash is the most economical, TLC (triple-level-cell) offers better performance and reliability to cover a variety of the mainstream storage applications. Both QLC and TLC will continue to coexist, as they’re each well-suited to specific applications.
例如，QLC更适合阅读密集型应用程序，而TLC更适合于高性能的混合工作量和写入密集型应用程序。只要存在QLC和TLC性能和可靠性之间的差异，QLC就不太可能完全替代TLC。
2. While getting denser and cheaper, 3D flash isn’t getting faster.
Generation over generation, 3D flash continues to increase in density and performance while becoming less expensive. New design strategies and features are being implemented to boost performance. For example, increasing the number of planes and new features such as virtual multi-LUN (VML) read, where each plane can be read independently at any time, increases random read IOPS. In addition, new standard specifications such as Toggle DDR5 push NAND interface speed up to 2.4 Gb/s.
3. Data will always live on hard-disk drives because they have the lowest cost per bit.
Usually, the technology offering the lowest cost wins in the long term. Hard drives continue to offer the lowest cost per stored bit, but solid-state storage is closing the gap due to data retrieval time.
SSDs will steadily grow in market share due to increasing density, lower cost per bit, and performance per capacity. This is an important metric because as drive capacity grows, but read and write performance can’t scale, then total IOPS per gigabyte worsens and the number of total users per drive becomes bottlenecked.
4. Serial interfaces are replacing parallel interfaces at all levels of design.
For I/O interfaces, this has definitely been a long-term trend: PATA to SATA, PCI to PCI Express, eMMC (embedded MultiMediaCard) to UFS (Universal Flash Storage). But for raw memory interfaces, it’s more of a mixed bag.
确实，平行或闪光灯主要被串行或闪光灯替换，但DRAM和NAND Flash维护了他们的多端宽巴士。在可预见的将来，实施非常高速的I/O电路的延迟和成本很可能会阻止在DRAM或NAND上采用高速串行。
5.托管NAND（EMMC，UFS，PCIE SSD）始终比RAW NAND更好。
NAND flash memory with a controller (managed NAND) continues to be the easiest-to-use solid-state storage device because it’s a complete non-volatile storage system. Using raw NAND flash requires management done by the host processor or controller chip: logical-to-physical block translation, bad-block managements, and error correction. Therefore, managed NAND will be easier to use since it presents itself as an ideal block storage device to the system.
然而,原始NAND将它的位置。例如, it would not make sense to build an SSD or flash array out of managed NAND devices due to the increased cost and lower performance thanks to increased latency from cascaded controllers.
NAND最好作为一个黑盒存储管理ubsystem. However, sometimes you need the flexibility to implement your own storage subsystem for performance or cost reasons, in which case utilizing raw NAND memory with your own architecture and firmware is the only way to go.
6. SD and microSD cards will lose their dominance as a removable storage form factor in two short years.
The SD card (along with microSD) has long been the most widely used memory form factor in the world. Recently, demand from high-resolution recordings and 5G mobile applications requiring higher bandwidth has surfaced, and new form factors supporting PCIe and NVMe are being developed. These new form factors, such as KIOXIA’s XFMEXPRESS, are now close to being standardized, meaning that much faster performance than the legacy SD interface is close at hand.
话虽如此，SD/MICROSD卡不会很快消失。根本没有其他形式更为接受或很小。
7. ECC performed internally in the memory is more efficient than the ECC handled by the host controller.
错误纠正代码（ECC）是一种正向错误校正的一种形式，其中计算检查位并添加到用户希望存储的数据中。然后，用户数据和ECC存储在存储介质上；在这种情况下，NAND闪存芯片。读数时检测到发生的误差位，可以根据ECC的强度和误差位数量进行校正。但是，所有这些都具有处理能力 - 首先要在存储前计算检查位，其次是在读数时纠正错误位。
But where should the ECC be done? On the memory die, or on a controller chip? The answer is: It depends. If the number of NAND dies required is one, then having ECC circuitry on the NAND die itself is convenient because it makes the NAND look error-free.
当连接到为智能设备和IoT设备供电的较小的微控制器时，这非常有用，因为这些处理器中的许多处理器缺少用于ECC引擎的硬件，并且在软件中进行ECC的硬件相对较慢且效率低下。此外，带有内置ECC的NAND可以使用较新的NAND光刻和较旧的处理器，而较旧的处理器不支持较新的较小的NAND几何形状的更高的ECC要求。
On the other hand, if the total number of NAND dies required in the application is higher, it makes economic sense to not burden every NAND die with the overhead of ECC circuitry and simply put the ECC engine in the controller. Higher processing speed is usually possible since the controller will be designed using a logic process versus a memory process. In an SSD, with one controller connected to many NAND die, the overall design will be less expensive if there’s one ECC engine in the controller.
8. UFS并不比EMMC快得多。
Actually, it is.
确实，由于某些瓶颈，很难以EMMC和UFS的最大接口速度操作，但实际的性能差异很大。UFS Ver3.1在2320 Mb/s时的最大接口速度约为400 MB/s的EMMC Ver5.1的六倍。尽管EMMC和UFS零件的实际性能低于此，但仍然存在很大的差异。
例如, we may see eMMC sequential read speeds of around 325 MB/s, while that of UFS is over 2000 MB/s. Moreover, large differences in performance are found for sequential write and random read and write as well.
9. The best design-in option is always the latest version of UFS over eMMC.
虽然UFS v3.1确实为EMMC/UFS提供了最佳性能，但要考虑的许多因素可能不会使其成为可行的选择。所需的内存密度可能是一个重要因素。为了利用UFS更快的接口，设备中需要多个模具才能交织。因此，UFS通常不支持少于32 GB的密度。这意味着我们可以期望仅需要4、8或16 GB的应用程序继续使用EMMC。
这在某些密度支持的UFS版本中也起着作用。在v2.1中，通常继续支持32-和64-GB UF。这是因为到v3.0/3.1界面出现时，可用的最小3D模具密度太大，无法使多个模具在这些密度下交织，无法利用更快的接口。实际上，如果使用较新的32或64 GB UFS设备构建32或64-GB UFS设备，这将导致性能降低。
As the layer count for 3D flash die increases each generation, the minimum die density increases for that generation, too. What interface the SoC supports is another factor, among others.
10. eMMC/UFS endurance can be specified in terabytes written (TBW).
TBW is the total amount of terabytes that can reliably be written to the flash device over its lifetime. This is a popular endurance specification for SSDs, and some entities are also starting to specify or request TBW as an endurance capability for eMMC and UFS.
但是，TBW作为规范不能准确地依靠以了解实际能够写入设备的数量。这是因为该规范忽略了写入放大的说明，从而降低了写入数量。并写入放大因主机处理器的访问模式而异。
A designer should work with the flash supplier to understand how the access pattern for their application's use case impacts the true endurance capability of the flash device, and how to potentially optimize the access pattern to the flash device to extend its longevity.
11.由于EMMC和UFS是JEDEC标准，因此不同供应商的零件之间的性能和可靠性几乎相同。
While managed flash (eMMC/UFS) will take care of fundamental tasks, the actual implementation can vary significantly from vendor to vendor. For instance, the frequency and algorithm by which garbage collection is performed needs to be optimized, since each operation temporarily reduces performance and adds write amplification. How wear leveling is performed, for example when the device is partitioned between native and enhanced mode, is another factor impacting the life of the device.
There are often important differences in performance and reliability, and tradeoffs need to be considered when comparing different vendors’ eMMC and UFS devices. Typically, suppliers who develop their own eMMC or UFS controllers in-house have better results, because they’re able to optimize their controller to work with their latest generation of flash.
