Analog-to-digital converters (ADCs) are the critical interface between the real world of sensors and signals and the digitized, processor- and software-driven system. Given their countless operating scenarios, it’s not surprising that thousands of distinct such converters are available from dozens of sources, with each one offering a blend of performance, packaging, power, and price attributes to be best-matched to the application priorities.
The right ADC can make a system design flow smoothly, while one that’s a lesser fit may require either performance compromises or significant effort to overcome its inadequacies—if that’s even possible. Vendors continue to add new ADCs to their roster to fit applications, take advantage of IC design advances, and leverage process improvement.
在最新的发行浪潮中（是的，新的ADC不断以快速的速度出现）是模拟设备的AD4630-24, a two-channel, simultaneous-sampling, 2-Msample/s successive-approximation-register (SAR) ADC(Fig. 1). With a guaranteed maximum ±0.9-ppm integral nonlinearity (INL) and no missing codes at 24 bits, the AD4630-24 achieves extreme precision from −40 to +125°C.
但是，仅这些规格和类似的规格并不能完全表征该转换器。ADI拥有该设备，包括其专利的易于驱动技术和多功能SPI串行外围界面（SPI），以最大程度地减少系统设计挑战并扩大直接兼容伴侣产品的选择。（当然，没有供应商承认他们的产品很难使用 - 这都是相对程度的问题。）
该公司坚持认为，EasyDrive方法可以确保性能，同时消除许多传统的系统级设计挑战，例如严格的布局指南。此外，FlexI-SPI数字界面通过提供易于结识的定时要求来帮助与主机处理器平滑ADC集成。
宽的差分输入和共同模式范围允许输入使用完整的±VREFrange without saturating, simplifying signal-conditioning requirements and system calibration. Low-power operation is another benefit at 15 mW per channel at 2 Msamples/s and dropping down to 1.5 mW per channel at 10 ksamples/s.
Additional device attributes include:
- Typical accuracy performance to 0.1 part per million (ppm) and signal-to-noise ratio (SNR) value of 105.7 dB.
- Small solution size: 7- × 7-mm, 64-ball package with internal power-supply and reference capacitors to reduce system footprint and component count.
- Wide common-mode input range ensures compatibility with both single-ended and differential-input signal chains.
- A wide data-clocking window, multiple SDO lanes, and optional dual-data-rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 Msamples/s.
- Echo clock mode and ADC master clock mode relax the timing requirements and simplify the use of digital isolators.
The49-page datasheetprovides the expected minimum/maximum performance and absolute maximum specifications. In addition, numerous tables and graphs characterize behavior from many perspectives including, but not limited to, SNR and signal-to-noise and distortion (SINAD) versus input frequency(Fig. 2)and total harmonic distortion (THD) versus input frequency and amplitude(Fig. 3).
Further design support is provided via theEVAL-AD4630-24FMCZ Evaluation Board($199), which is designed for use with a Digilent ZedBoard used to control data capture and buffering(Fig. 4).
The evaluation board connects to the ZedBoard board via a field-programmable gate-array (FPGA) mezzanine card (FMC) low-pin-count (LPC) connector and includes a voltage reference, clock source, and ADC drivers. The ZedBoard connects to a PC through a USB interface.
ADC上有一个概述和链接到其他资源产品页面和一分钟的视频这里. The dual-channel AD4630-24 and single-channel AD4030-24 are available now ($30.95 in 1,000-piece lots); the four additional derivative SAR ADCs are expected later this year.
