本文是Electronics History系列：图形芯片编年史.
Reality Simulation Systems (RSSI) was founded in 1993 at Rensselaer Polytechnic Institute’s Venture Creations, RPI’s incubator in Troy, New York, by Mike Lewis and Steve Morein. The goal was to develop a very high-performance, cost-effective 3D graphics processor for the interactive electronic entertainment market.
该公司开发了一种名为Pixelsquirt的瓷砖设计。莫尔因（Morein）是该公司第一次芯片的首席设计师Microsoft’s Talisman projectand VideoLogic’s PowerVR.
在1994, Lewis and Morein moved to San Jose to be closer to the action in Silicon Valley. Lewis attracted interest from angel investors and, in 1995, was able to raise additional capital to enhance the design further.
Lewis and Morein said the 3D PixelSquirt architecture offered several improvements over traditional methods of 3D rendering. The architecture, said Lewis, addressed the bandwidth and memory requirements to achieve visual realism for 3D at 1024 × 768 and higher resolutions, the standard for high-resolution established by IBM in 1987 with the 8514/A.
Enter S-MOS
在1996, S-MOS Systems and RSSI announced a long-term development and marketing agreement to design 3D technology and products for personal computers. S-MOS worked with Steve Morein to develop the SPC1515 PIX.
Morein said at the time, “Even with the drop in memory prices it doesn’t pay to reinvent 2D. Instead, make it [the PIX] work with any card that supports DirectDraw surfaces.” When asked if the engineering team would take advantage of Tseng’s IMA port, Morein remarked they were investigating this method.
When asked about competitors, Sandeep Gupta of S-MOS said, “Rendition, maybe, but the real competition is a pair of skates for a Christmas present.”
RSSI避免lookup-write背上CPU,它instead used 250 kB of on-chip cache. It also developed special-purpose code that could take advantage of the Pentium’s dual pipeline, similar to a traditional image generator. Morein said the next version of the chip would tap AGP (Accelerated Graphics Port).
The SCP1515 performed point-sampled texel-address calculations for texture mapping and supported 32 × 32 to 1024 × 1024 resolution maps. Textures were stored in the host-system memory, and the chip managed 65,536 separate texture maps and up to 128 MB of addressable texture-map data. PIX also supported PCI burst transfers.
When asked about comparisons to thestreaming processor conceptof Talisman, Morein said, “We started with tile and rejected it. They do a nice job, but it’s better if you don’t have to use them. We do texture lookup after visibility. Render into texture maps, then software texture lookup.”
莫尔因说，它能够维持比PCI超过100 MB/s的数据传输率，但它与插入任何“不准备”命令的VGA芯片无法使用。芯片以66 mpixels/s的速度运行（Z-Buffered，640×480）。在800×600时，芯片达到45 mpixels/s。
Under the terms of the agreement, S-MOS would provide the manufacturing through its affiliate, Seiko Epson in Japan, while also offering worldwide sales, marketing, and co-development resources. RSSI would provide key technology and design expertise in all phases of development. The partnership was a breakthrough and validation for RSSI.
Seiko was (and still is) a very well-respected precision technology company, and the Japanese are highly diligent in their partnerships. The last thing the 115-year-old company wanted was to be embarrassed or have its reputation damaged.
Tom Endicott, vice president of S-MOS marketing and sales, said, “We chose to work with RSSI because of their unique and innovative approach to three-dimensional design for personal computers and their specific knowledge of the computer games market. While others were approaching the problem of 3D graphics from a workstation point of view, RSSI approached the problem from the PC user’s point of view.”
The first chip of a planned three to come out of the agreement was the SPC1515 or PIX (PixelSquirt). S-MOS announced it was targeting video games and VRML 3D. Lewis said S-MOS would use existing 2D graphics subsystem buffer memory and main memory to reduce cost and improve performance. When S-MOS forecasted the bill-of-material (BOM), it said it would cost $60 for a 3D upgrade board with the PIX. That was an aggressive price for the market segment the company was targeting. But as it turned out, it was not realizable.
S-MOS introduced the concept for the graphics chip at the 1996 Computer Game Developers Conference. The firm was optimistic it would have a motherboard design win to announce soon. But it never made it into production.
RSSI: PixelSquirt
RSSI的无框架 - 弱势Pixelsquirt在1995年的CGDC上首次亮相。在会议上，RSSI总裁戴维·伯恩斯坦（David Bernstein）表示：“我们与S-MOS的关系创造了出色的工作伙伴关系，以使我们的灵活3D图形技术的完整开发和介绍。RSSI设计的简单性与S-MOS的一流制造设施相结合，按照PC Marketplace的要求，将允许非常快速的产品周期。”
RSSI developed a scalable image generator. High-performance visualization and simulation systems like flight simulators used image generators. For increased performance, it was possible to daisy-chain several PixelSquirts together.
该公司构建了一个带有四个Pixelsquirts和一个主控制器的板载（AIB）。AIB通过功能连接器从VGA板上接受了视频流，然后对多边形进行了阴影。它通过PCI总线吸入多边形边缘信息。它以100,000平面为400像素三角形/s的渲染，具有超过3-gpixel/s的填充率。
AIB可以每帧提供2,000个三角形，而与帧速率无关。AIB提供了24位颜色，带有1位Alpha平面和24位Z-Buffer。芯片支持的分辨率最高为1024×768。
RSSI offered the four PixelSquirts, with a DAC and a master controller chip on an AIB they called LittleSquirt, with an estimated price of less than $500. Although the AIB was not appropriate for gamers’ budgets, the design showed off the company’s capabilities, and the price was cheaper than standard image generators. But, even with S-MOS’s support, military and commercial aircraft companies balked at working with such a small company. As has been proven too many times, big companies like to deal with big companies.
在mid-1997, the company began work on a new architecture, Aquila PX, and teased an announcement for March 1998.
Aquila PX offered high-performance 2D, 3D, and video and simultaneous NTSC/PAL television output. Lewis said the design would deliver 100 Mpixels/s. It had a floating-point setup engine, a 4K texture cache, a 230-MHz LUT-DAC, and a nonlinear three-line flicker filter for television output. Lewis said Aquila PX supported a 1024 × 768 × 16 resolution with a 1-MB texture buffer in a 4-MB configuration.
后续芯片velatx是刘易斯（Lewis）声称可以达到250 mpixels/s的仅3D处理器，并且结合了许多高级3D功能，例如各向异性纹理。刘易斯声称，Velatx将与任何现有的2D图形加速器合作。两种设备的3D核心都可以进行许可。
在1997, Morein left RSSI and moved toamd. Aquila PX never made it out of the laboratory. But in 1998, the company announced its VelaTX.
Stellar Is Born（1997）
1997年底，RSSI重组并更名为恒星半导体。在Sky Capital的协助下，Stellar购买了RSSI的资产，其中包括针对新的3D芯片代码名称Aquila PX的设计。一些高管离开了S-MOS系统，以帮助建立包括Sandeep Gupta在内的公司。Gupta曾是S-MOS的图形产品高级产品经理，并成为Stellar的首席执行官。工程副总裁兼Stellar联合创始人Joseph C. Del Rio是S-MOS工程执行董事。该公司的首席技术官迈克尔·刘易斯（Michael Lewis）在搬到Stellar之前就在RSSI。
该公司于1998年在加利福尼亚州圣克拉拉的电子研讨会（IP98）举行的知识产权上启动。该公司当时拥有25多名员工，并完成了两轮风险融资。当时，S-MOS仍在追求自己的课程。
Due to pending patent applications, scant details were available at the time. Gupta said the design would achieve high performance, high resolution, and high-quality realism. Furthermore, the architecture (like Talisman and PowerVR) did not use a Z-buffer, and it featured a real-time data flow while using half the gates of alternative solutions. The architecture was developed in 1993 and was implemented in an AIB a year later.
Stellar planned to develop intellectual property (IP) for a 3D graphics engine. “We also plan to move into the fabless semiconductor business by creating, marketing, and selling graphics engines for the add-in card and motherboard desktop PC arena,” said Gupta. However, Gupta added that the Stellar graphics accelerator would target a niche market in the 3D space, one not well-served by other graphics companies.
Stellar had two licensees signed up for its 3D core but would not comment on who they were. Broadcom was most likely one of them.
The company planned to introduce a proprietary 3D graphics engine in the second quarter of 1998 as a synthesized HDL netlist, and it claimed to have two foundries qualified to build it.
The first 3D core was DirectX 5.0 compliant, and the company said it would use less than 250,000 gates and be synthesizable up to 100 MHz. Stellar claimed to have proven the core twice in silicon with software drivers using Direct3D and OpenGL. Gupta said it would take Stellar less than a week to hook the existing 3D core design into a company’s device. “Because the architecture is pipelined, a company can balance the performance loading and host interface effectively,” he added.
The 3D IP core and the graphics chips used RSSI’s original PixelSquirt architecture based on a parallel processor and a multiple pipelined design. PixelSquirt’s tiling engine eliminated the need for Z-buffering because it removed hidden surfaces before filtering, texture mapping, and atmospheric conditioning.
Stellar said a key advantage of its core was the ability to interface easily to existing host interface and memory controller blocks. In those cases, the host IF block was only required to provide a bus master read connection to the host CPU, and the memory controller only needed to provide a read/write interface to the memory for texture map storage. The company said the 3D core was small and highly scalable, and it offered a range of price and performance options to licensees. Stellar had five patents in prosecution at the time.
VelaTX (1998)
Stellar described VelaTX as the first of a family of 3D rendering engines based on the PixelSquirt architecture. The company claimed it would deliver 200-Mpixel/s rendering without Z-buffering. Z-buffer elimination, said Stellar, reduces the requirement for fast memory. Previously, PixelSquirt had been offered as a synthesizable core.
在stead of rendering one polygon at a time, the PixelSquirt rendered a pixel at a time in raster order, starting with 24-bit floating-point hidden-surface removal. The remaining operations act only on data output to the screen.
The chip had 2.5 MB of DRAM integrated with the renderer via a 512-bit bus to speed up texture mapping. Further texture storage used external SDRAM of up to 8 MB. Stellar said VelaTX would support numerous Open GL and DirectX 6 features in hardware, including perspective correction, specular highlighting, alpha-blend and texture-blend modes, multiple fog modes, and texture compression.
该设计具有AGP-TO-PCI桥，P-Pipe，VIP/VMI端口和一个内存膨胀总线，使芯片可以形成用于多媒体扩展AIB的枢纽。Velatx包装在388针BGA中，价格为10,000美元，价格为35美元。Stellar表示，它将在1998年第四季度或1999年第一季度提供。
Stellar and Sican（1999）
在1999年电子研讨会（IP99）的知识产权上，Stellar和Sican GmbH（德国汉诺威）宣布了营销和销售协议。Sican同意与SICAN现有的核心产品图书馆一起销售和出售Stellar的IP核心。SICAN还将为Stellar的客户群提供设计服务。
SICAN设计副总裁Valentin von Tils表示，两家公司的IP核心产品将相互补充。SICAN提供音频和视频解码，宽带媒体访问和公交界面核心。在混音中添加图形为SICAN提供了更大的占地面积，在多媒体，通信和网络应用程序段中。
冯·泰尔斯（Von Tils）补充说：“我们的综合力量将极大地增强SICAN的能力，为在欧洲设计系统中设计系统解决方案的客户提供强大的核心。”这笔交易看起来很合适，但这将是短暂的。
Broadcom Buys Stellar (2000)
After several months of negotiations,Broadcomannounced it would acquire Stellar Semiconductor to help the maker of high-speed communications chips move into set-top-box (STB) and handheld internet appliance markets. “This acquisition provides Broadcom with an important piece of technology required to deliver high-end 3D games to digital set-top boxes,” said Broadcom CEO Henry Nicholas.
“After working with Broadcom for nearly a year, we’re excited about combining forces to address the burgeoning consumer digital entertainment market,” said Gupta.
Broadcom said it would account for the acquisition as a pooling of interest. A one-time charge would be taken in the first quarter to cover the expense related to the transaction.
Broadcom attempted to use the Stellar technology in an STB chip, but it struggled to find many OEMs willing to pay the price for the performance boost. In addition, cable companies did not have the content—or the bandwidth—to make good use of the Stellar technology back then. Lewis left Broadcom a few years later and, in 2015, started Mycroft AI, an open-source equivalent to Amazon Echo and Google Home.
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